The ENIAC JU project ELESIS aims to define and standardise built-in chip test features with a common interface that will enable the identification of faults relatively inexpensively and thus reduce production costs.| www.eniac.eu/web/downloads/projectprofiles/pp_call4_elesis.pdf| http://www.rvo.nl/subsidies-regelingen/point-one| www.eniac.eu/web/index.php